// Verilog netlist produced by program LSE :  version Diamond (64-bit) 3.6.0.83.4
// Netlist written on Tue Aug 30 11:34:24 2016
//
// Verilog Description of module ip_gddr71tx_12lane
//

module ip_gddr71tx_12lane (clkout, ready, refclk, sclk, start, sync_clk, 
            sync_reset, data0, data1, data10, data11, data2, data3, 
            data4, data5, data6, data7, data8, data9, dout) /* synthesis NGD_DRC_MASK=1, syn_module_defined=1 */ ;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(215[8:26])
    output clkout /* synthesis black_box_pad_pin=1 */ ;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(234[17:23])
    output ready;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(235[17:22])
    input refclk;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(218[16:22])
    output sclk;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(236[17:21])
    input start;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(219[16:21])
    input sync_clk;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(220[16:24])
    input sync_reset;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(221[16:26])
    input [6:0]data0;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(222[22:27])
    input [6:0]data1;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(223[22:27])
    input [6:0]data10;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(224[22:28])
    input [6:0]data11;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(225[22:28])
    input [6:0]data2;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(226[22:27])
    input [6:0]data3;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(227[22:27])
    input [6:0]data4;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(228[22:27])
    input [6:0]data5;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(229[22:27])
    input [6:0]data6;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(230[22:27])
    input [6:0]data7;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(231[22:27])
    input [6:0]data8;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(232[22:27])
    input [6:0]data9;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(233[22:27])
    output [11:0]dout;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(237[24:28])
    
    wire refclk /* synthesis is_clock=1 */ ;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(218[16:22])
    wire sync_clk /* synthesis SET_AS_NETWORK=sync_clk, is_clock=1 */ ;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(220[16:24])
    wire sclk /* synthesis is_clock=1, SET_AS_NETWORK=sclk */ ;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(236[17:21])
    wire eclko /* synthesis is_clock=1 */ ;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(342[10:15])
    
    wire buf_clkout, preamble1, scuba_vhi, buf_douto11, buf_douto10, 
        buf_douto9, buf_douto8, buf_douto7, buf_douto6, buf_douto5, 
        buf_douto4, buf_douto3, buf_douto2, buf_douto1, buf_douto0, 
        scuba_vlo, reset, stop, n565;
    
    OB Inst7_OB (.I(buf_clkout), .O(clkout)) /* synthesis IO_TYPE="LVDS", syn_instantiated=1 */ ;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(351[8:45])
    ODDR71B Inst6_ODDR71B (.D0(preamble1), .D1(preamble1), .D2(scuba_vlo), 
            .D3(scuba_vlo), .D4(scuba_vlo), .D5(scuba_vhi), .D6(scuba_vhi), 
            .ECLK(eclko), .SCLK(sclk), .RST(reset), .Q(buf_clkout)) /* synthesis syn_instantiated=1 */ ;
    defparam Inst6_ODDR71B.GSR = "ENABLED";
    ODDR71B Inst5_ODDR71B11 (.D0(data11[0]), .D1(data11[1]), .D2(data11[2]), 
            .D3(data11[3]), .D4(data11[4]), .D5(data11[5]), .D6(data11[6]), 
            .ECLK(eclko), .SCLK(sclk), .RST(reset), .Q(buf_douto11)) /* synthesis syn_instantiated=1 */ ;
    defparam Inst5_ODDR71B11.GSR = "ENABLED";
    ODDR71B Inst5_ODDR71B10 (.D0(data10[0]), .D1(data10[1]), .D2(data10[2]), 
            .D3(data10[3]), .D4(data10[4]), .D5(data10[5]), .D6(data10[6]), 
            .ECLK(eclko), .SCLK(sclk), .RST(reset), .Q(buf_douto10)) /* synthesis syn_instantiated=1 */ ;
    defparam Inst5_ODDR71B10.GSR = "ENABLED";
    ODDR71B Inst5_ODDR71B9 (.D0(data9[0]), .D1(data9[1]), .D2(data9[2]), 
            .D3(data9[3]), .D4(data9[4]), .D5(data9[5]), .D6(data9[6]), 
            .ECLK(eclko), .SCLK(sclk), .RST(reset), .Q(buf_douto9)) /* synthesis syn_instantiated=1 */ ;
    defparam Inst5_ODDR71B9.GSR = "ENABLED";
    ODDR71B Inst5_ODDR71B8 (.D0(data8[0]), .D1(data8[1]), .D2(data8[2]), 
            .D3(data8[3]), .D4(data8[4]), .D5(data8[5]), .D6(data8[6]), 
            .ECLK(eclko), .SCLK(sclk), .RST(reset), .Q(buf_douto8)) /* synthesis syn_instantiated=1 */ ;
    defparam Inst5_ODDR71B8.GSR = "ENABLED";
    ODDR71B Inst5_ODDR71B7 (.D0(data7[0]), .D1(data7[1]), .D2(data7[2]), 
            .D3(data7[3]), .D4(data7[4]), .D5(data7[5]), .D6(data7[6]), 
            .ECLK(eclko), .SCLK(sclk), .RST(reset), .Q(buf_douto7)) /* synthesis syn_instantiated=1 */ ;
    defparam Inst5_ODDR71B7.GSR = "ENABLED";
    ODDR71B Inst5_ODDR71B6 (.D0(data6[0]), .D1(data6[1]), .D2(data6[2]), 
            .D3(data6[3]), .D4(data6[4]), .D5(data6[5]), .D6(data6[6]), 
            .ECLK(eclko), .SCLK(sclk), .RST(reset), .Q(buf_douto6)) /* synthesis syn_instantiated=1 */ ;
    defparam Inst5_ODDR71B6.GSR = "ENABLED";
    ODDR71B Inst5_ODDR71B5 (.D0(data5[0]), .D1(data5[1]), .D2(data5[2]), 
            .D3(data5[3]), .D4(data5[4]), .D5(data5[5]), .D6(data5[6]), 
            .ECLK(eclko), .SCLK(sclk), .RST(reset), .Q(buf_douto5)) /* synthesis syn_instantiated=1 */ ;
    defparam Inst5_ODDR71B5.GSR = "ENABLED";
    ODDR71B Inst5_ODDR71B4 (.D0(data4[0]), .D1(data4[1]), .D2(data4[2]), 
            .D3(data4[3]), .D4(data4[4]), .D5(data4[5]), .D6(data4[6]), 
            .ECLK(eclko), .SCLK(sclk), .RST(reset), .Q(buf_douto4)) /* synthesis syn_instantiated=1 */ ;
    defparam Inst5_ODDR71B4.GSR = "ENABLED";
    ODDR71B Inst5_ODDR71B3 (.D0(data3[0]), .D1(data3[1]), .D2(data3[2]), 
            .D3(data3[3]), .D4(data3[4]), .D5(data3[5]), .D6(data3[6]), 
            .ECLK(eclko), .SCLK(sclk), .RST(reset), .Q(buf_douto3)) /* synthesis syn_instantiated=1 */ ;
    defparam Inst5_ODDR71B3.GSR = "ENABLED";
    ODDR71B Inst5_ODDR71B2 (.D0(data2[0]), .D1(data2[1]), .D2(data2[2]), 
            .D3(data2[3]), .D4(data2[4]), .D5(data2[5]), .D6(data2[6]), 
            .ECLK(eclko), .SCLK(sclk), .RST(reset), .Q(buf_douto2)) /* synthesis syn_instantiated=1 */ ;
    defparam Inst5_ODDR71B2.GSR = "ENABLED";
    ODDR71B Inst5_ODDR71B1 (.D0(data1[0]), .D1(data1[1]), .D2(data1[2]), 
            .D3(data1[3]), .D4(data1[4]), .D5(data1[5]), .D6(data1[6]), 
            .ECLK(eclko), .SCLK(sclk), .RST(reset), .Q(buf_douto1)) /* synthesis syn_instantiated=1 */ ;
    defparam Inst5_ODDR71B1.GSR = "ENABLED";
    ODDR71B Inst5_ODDR71B0 (.D0(data0[0]), .D1(data0[1]), .D2(data0[2]), 
            .D3(data0[3]), .D4(data0[4]), .D5(data0[5]), .D6(data0[6]), 
            .ECLK(eclko), .SCLK(sclk), .RST(reset), .Q(buf_douto0)) /* synthesis syn_instantiated=1 */ ;
    defparam Inst5_ODDR71B0.GSR = "ENABLED";
    VHI scuba_vhi_inst (.Z(scuba_vhi));
    FD1S3DX Inst4_FD1S3DX (.D(scuba_vhi), .CK(sclk), .CD(reset), .Q(preamble1)) /* synthesis syn_instantiated=1 */ ;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(408[13:82])
    defparam Inst4_FD1S3DX.GSR = "ENABLED";
    OB Inst3_OB11 (.I(buf_douto11), .O(dout[11])) /* synthesis IO_TYPE="LVDS", syn_instantiated=1 */ ;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(410[8:50])
    OB Inst3_OB10 (.I(buf_douto10), .O(dout[10])) /* synthesis IO_TYPE="LVDS", syn_instantiated=1 */ ;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(413[8:50])
    OB Inst3_OB9 (.I(buf_douto9), .O(dout[9])) /* synthesis IO_TYPE="LVDS", syn_instantiated=1 */ ;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(416[8:47])
    OB Inst3_OB8 (.I(buf_douto8), .O(dout[8])) /* synthesis IO_TYPE="LVDS", syn_instantiated=1 */ ;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(419[8:47])
    OB Inst3_OB7 (.I(buf_douto7), .O(dout[7])) /* synthesis IO_TYPE="LVDS", syn_instantiated=1 */ ;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(422[8:47])
    OB Inst3_OB6 (.I(buf_douto6), .O(dout[6])) /* synthesis IO_TYPE="LVDS", syn_instantiated=1 */ ;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(425[8:47])
    OB Inst3_OB5 (.I(buf_douto5), .O(dout[5])) /* synthesis IO_TYPE="LVDS", syn_instantiated=1 */ ;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(428[8:47])
    OB Inst3_OB4 (.I(buf_douto4), .O(dout[4])) /* synthesis IO_TYPE="LVDS", syn_instantiated=1 */ ;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(431[8:47])
    OB Inst3_OB3 (.I(buf_douto3), .O(dout[3])) /* synthesis IO_TYPE="LVDS", syn_instantiated=1 */ ;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(434[8:47])
    OB Inst3_OB2 (.I(buf_douto2), .O(dout[2])) /* synthesis IO_TYPE="LVDS", syn_instantiated=1 */ ;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(437[8:47])
    OB Inst3_OB1 (.I(buf_douto1), .O(dout[1])) /* synthesis IO_TYPE="LVDS", syn_instantiated=1 */ ;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(440[8:47])
    OB Inst3_OB0 (.I(buf_douto0), .O(dout[0])) /* synthesis IO_TYPE="LVDS", syn_instantiated=1 */ ;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(443[8:47])
    VLO scuba_vlo_inst (.Z(scuba_vlo));
    CLKDIVF Inst2_CLKDIVF (.CLKI(eclko), .RST(reset), .ALIGNWD(scuba_vlo), 
            .CDIVX(sclk)) /* synthesis syn_instantiated=1 */ ;
    defparam Inst2_CLKDIVF.GSR = "DISABLED";
    defparam Inst2_CLKDIVF.DIV = "3.5";
    ECLKSYNCB Inst1_ECLKSYNCB (.ECLKI(refclk), .STOP(stop), .ECLKO(eclko)) /* synthesis syn_instantiated=1 */ ;
    PUR PUR_INST (.PUR(scuba_vhi));
    defparam PUR_INST.RST_PULSE = 1;
    GSR GSR_INST (.GSR(scuba_vhi));
    LUT4 m0_lut (.Z(n565)) /* synthesis lut_function=0, syn_instantiated=1 */ ;
    defparam m0_lut.init = 16'h0000;
    ip_gddr71tx_12lanegddr_sync Inst_gddr_sync (.cs_gddr_sync({ready, Open_0, 
            stop}), .\ns_gddr_sync_2__N_22[2] (start), .sync_clk(sync_clk), 
            .sync_reset(sync_reset), .reset(reset), .n565(n565)) /* synthesis syn_module_defined=1 */ ;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(348[33] 349[70])
    
endmodule
//
// Verilog Description of module PUR
// module not written out since it is a black-box. 
//

//
// Verilog Description of module ip_gddr71tx_12lanegddr_sync
//

module ip_gddr71tx_12lanegddr_sync (cs_gddr_sync, \ns_gddr_sync_2__N_22[2] , 
            sync_clk, sync_reset, reset, n565) /* synthesis syn_module_defined=1 */ ;
    output [2:0]cs_gddr_sync;
    input \ns_gddr_sync_2__N_22[2] ;
    input sync_clk;
    input sync_reset;
    output reset;
    input n565;
    
    wire sync_clk /* synthesis SET_AS_NETWORK=sync_clk, is_clock=1 */ ;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(220[16:24])
    
    wire n174;
    wire [2:0]n74;
    
    wire n551;
    wire [3:0]ctrl_cnt;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(77[13:21])
    
    wire n552, n172;
    wire [3:0]n14;
    wire [2:0]stop_assert;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(78[13:24])
    
    wire n545;
    wire [2:0]ns_gddr_sync_2__N_13;
    
    wire n1;
    wire [2:0]cs_gddr_sync_c;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(79[13:25])
    
    wire reset_flag, n550;
    wire [2:0]ns_gddr_sync_2__N_19;
    
    wire n547;
    wire [2:0]n17;
    
    wire sync_clk_enable_4, ddr_reset_d, n546, sync_clk_enable_5, sync_clk_enable_6, 
        stop_assert_2__N_48, n548, n549;
    
    LUT4 i2_3_lut (.A(cs_gddr_sync[2]), .B(n174), .C(cs_gddr_sync[0]), 
         .Z(n74[1])) /* synthesis lut_function=(!(A+!(B (C)))) */ ;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(143[3] 208[10])
    defparam i2_3_lut.init = 16'h4040;
    LUT4 scuba_vlo_bdd_2_lut_462 (.A(n551), .B(ctrl_cnt[0]), .Z(n552)) /* synthesis lut_function=(A (B)) */ ;
    defparam scuba_vlo_bdd_2_lut_462.init = 16'h8888;
    LUT4 i217_3_lut_3_lut (.A(ctrl_cnt[3]), .B(n172), .C(ctrl_cnt[0]), 
         .Z(n14[0])) /* synthesis lut_function=(A (B (C))+!A !((C)+!B)) */ ;
    defparam i217_3_lut_3_lut.init = 16'h8484;
    LUT4 i3_3_lut_4_lut (.A(stop_assert[1]), .B(n545), .C(stop_assert[0]), 
         .D(\ns_gddr_sync_2__N_22[2] ), .Z(ns_gddr_sync_2__N_13[0])) /* synthesis lut_function=(!((B+!(C (D)))+!A)) */ ;
    defparam i3_3_lut_4_lut.init = 16'h2000;
    LUT4 i2_3_lut_adj_14 (.A(cs_gddr_sync[2]), .B(n1), .C(cs_gddr_sync_c[1]), 
         .Z(n74[0])) /* synthesis lut_function=(!(A+((C)+!B))) */ ;
    defparam i2_3_lut_adj_14.init = 16'h0404;
    FD1S3DX reset_flag_65 (.D(n550), .CK(sync_clk), .CD(sync_reset), .Q(reset_flag));   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(105[3] 137[6])
    defparam reset_flag_65.GSR = "ENABLED";
    LUT4 mux_36_Mux_0_i1_4_lut (.A(ns_gddr_sync_2__N_13[0]), .B(reset_flag), 
         .C(cs_gddr_sync[0]), .D(ns_gddr_sync_2__N_19[1]), .Z(n1)) /* synthesis lut_function=(A (((D)+!C)+!B)+!A (B (C (D))+!B (C))) */ ;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(143[3] 208[10])
    defparam mux_36_Mux_0_i1_4_lut.init = 16'hfa3a;
    LUT4 i1_2_lut_rep_15 (.A(cs_gddr_sync[0]), .B(cs_gddr_sync_c[1]), .Z(n547)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i1_2_lut_rep_15.init = 16'heeee;
    FD1S3DX ctrl_cnt__i0 (.D(n14[0]), .CK(sync_clk), .CD(sync_reset), 
            .Q(ctrl_cnt[0])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=33, LSE_RCOL=70, LSE_LLINE=348, LSE_RLINE=349 */ ;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(105[3] 137[6])
    defparam ctrl_cnt__i0.GSR = "ENABLED";
    LUT4 i247_1_lut (.A(stop_assert[0]), .Z(n17[0])) /* synthesis lut_function=(!(A)) */ ;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(123[22:37])
    defparam i247_1_lut.init = 16'h5555;
    LUT4 i249_2_lut (.A(stop_assert[1]), .B(stop_assert[0]), .Z(n17[1])) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(123[22:37])
    defparam i249_2_lut.init = 16'h6666;
    LUT4 i13_4_lut_3_lut (.A(cs_gddr_sync[0]), .B(cs_gddr_sync_c[1]), .C(cs_gddr_sync[2]), 
         .Z(sync_clk_enable_4)) /* synthesis lut_function=(!(A (C)+!A (B))) */ ;
    defparam i13_4_lut_3_lut.init = 16'h1b1b;
    LUT4 i2_4_lut (.A(cs_gddr_sync[2]), .B(\ns_gddr_sync_2__N_22[2] ), .C(n552), 
         .D(n547), .Z(n74[2])) /* synthesis lut_function=(!(A ((D)+!B)+!A (((D)+!C)+!B))) */ ;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(143[3] 208[10])
    defparam i2_4_lut.init = 16'h00c8;
    LUT4 i256_3_lut (.A(stop_assert[2]), .B(stop_assert[1]), .C(stop_assert[0]), 
         .Z(n17[2])) /* synthesis lut_function=(!(A (B (C))+!A !(B (C)))) */ ;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(123[22:37])
    defparam i256_3_lut.init = 16'h6a6a;
    LUT4 cs_gddr_sync_1__I_0_2_lut (.A(cs_gddr_sync_c[1]), .B(ddr_reset_d), 
         .Z(reset)) /* synthesis lut_function=(A+(B)) */ ;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(89[20:49])
    defparam cs_gddr_sync_1__I_0_2_lut.init = 16'heeee;
    FD1P3DX cs_gddr_sync_i2 (.D(n74[2]), .SP(sync_clk_enable_4), .CK(sync_clk), 
            .CD(sync_reset), .Q(cs_gddr_sync[2])) /* synthesis syn_preserve=1, LSE_LINE_FILE_ID=5, LSE_LCOL=33, LSE_RCOL=70, LSE_LLINE=348, LSE_RLINE=349 */ ;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(105[3] 137[6])
    defparam cs_gddr_sync_i2.GSR = "ENABLED";
    LUT4 i79_2_lut_rep_14 (.A(ctrl_cnt[1]), .B(ctrl_cnt[0]), .Z(n546)) /* synthesis lut_function=(A (B)) */ ;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(117[19:31])
    defparam i79_2_lut_rep_14.init = 16'h8888;
    FD1S3BX ddr_reset_d_67 (.D(n565), .CK(sync_clk), .PD(sync_reset), 
            .Q(ddr_reset_d)) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=33, LSE_RCOL=70, LSE_LLINE=348, LSE_RLINE=349 */ ;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(105[3] 137[6])
    defparam ddr_reset_d_67.GSR = "ENABLED";
    LUT4 i2_3_lut_4_lut (.A(ctrl_cnt[1]), .B(ctrl_cnt[0]), .C(ctrl_cnt[3]), 
         .D(ctrl_cnt[2]), .Z(ns_gddr_sync_2__N_19[1])) /* synthesis lut_function=(((C+(D))+!B)+!A) */ ;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(117[19:31])
    defparam i2_3_lut_4_lut.init = 16'hfff7;
    FD1P3DX ctrl_cnt__i3 (.D(n14[3]), .SP(sync_clk_enable_5), .CK(sync_clk), 
            .CD(sync_reset), .Q(ctrl_cnt[3])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=33, LSE_RCOL=70, LSE_LLINE=348, LSE_RLINE=349 */ ;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(105[3] 137[6])
    defparam ctrl_cnt__i3.GSR = "ENABLED";
    LUT4 i225_2_lut_rep_13 (.A(reset_flag), .B(stop_assert[2]), .Z(n545)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i225_2_lut_rep_13.init = 16'heeee;
    LUT4 i222_4_lut (.A(ctrl_cnt[3]), .B(n172), .C(ctrl_cnt[2]), .D(n546), 
         .Z(n14[3])) /* synthesis lut_function=(!(A ((C (D))+!B)+!A !(B (C (D))))) */ ;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(105[3] 137[6])
    defparam i222_4_lut.init = 16'h4888;
    FD1P3DX ctrl_cnt__i2 (.D(n14[2]), .SP(sync_clk_enable_5), .CK(sync_clk), 
            .CD(sync_reset), .Q(ctrl_cnt[2])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=33, LSE_RCOL=70, LSE_LLINE=348, LSE_RLINE=349 */ ;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(105[3] 137[6])
    defparam ctrl_cnt__i2.GSR = "ENABLED";
    FD1P3DX cs_gddr_sync_i1 (.D(n74[1]), .SP(sync_clk_enable_4), .CK(sync_clk), 
            .CD(sync_reset), .Q(cs_gddr_sync_c[1])) /* synthesis syn_preserve=1, LSE_LINE_FILE_ID=5, LSE_LCOL=33, LSE_RCOL=70, LSE_LLINE=348, LSE_RLINE=349 */ ;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(105[3] 137[6])
    defparam cs_gddr_sync_i1.GSR = "ENABLED";
    LUT4 i346_3_lut (.A(cs_gddr_sync_c[1]), .B(cs_gddr_sync[0]), .C(cs_gddr_sync[2]), 
         .Z(sync_clk_enable_6)) /* synthesis lut_function=(!(A+(B (C)))) */ ;
    defparam i346_3_lut.init = 16'h1515;
    FD1P3DX ctrl_cnt__i1 (.D(n14[1]), .SP(sync_clk_enable_5), .CK(sync_clk), 
            .CD(sync_reset), .Q(ctrl_cnt[1])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=33, LSE_RCOL=70, LSE_LLINE=348, LSE_RLINE=349 */ ;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(105[3] 137[6])
    defparam ctrl_cnt__i1.GSR = "ENABLED";
    LUT4 i110_4_lut (.A(reset_flag), .B(ns_gddr_sync_2__N_19[1]), .C(cs_gddr_sync[2]), 
         .D(n547), .Z(n172)) /* synthesis lut_function=(A (B+!(C+(D)))+!A (B (C+(D)))) */ ;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(110[9] 111[33])
    defparam i110_4_lut.init = 16'hccca;
    LUT4 i223_3_lut_4_lut (.A(ctrl_cnt[1]), .B(ctrl_cnt[0]), .C(n172), 
         .D(ctrl_cnt[2]), .Z(n14[2])) /* synthesis lut_function=(!(A (B ((D)+!C)+!B !(C (D)))+!A !(C (D)))) */ ;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(117[19:31])
    defparam i223_3_lut_4_lut.init = 16'h7080;
    FD1P3DX stop_assert_58__i2 (.D(n17[2]), .SP(stop_assert_2__N_48), .CK(sync_clk), 
            .CD(sync_reset), .Q(stop_assert[2]));   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(123[22:37])
    defparam stop_assert_58__i2.GSR = "ENABLED";
    FD1P3DX stop_assert_58__i1 (.D(n17[1]), .SP(stop_assert_2__N_48), .CK(sync_clk), 
            .CD(sync_reset), .Q(stop_assert[1]));   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(123[22:37])
    defparam stop_assert_58__i1.GSR = "ENABLED";
    LUT4 i2_2_lut_3_lut (.A(reset_flag), .B(stop_assert[2]), .C(\ns_gddr_sync_2__N_22[2] ), 
         .Z(stop_assert_2__N_48)) /* synthesis lut_function=(!(A+(B+!(C)))) */ ;
    defparam i2_2_lut_3_lut.init = 16'h1010;
    FD1P3DX stop_assert_58__i0 (.D(n17[0]), .SP(stop_assert_2__N_48), .CK(sync_clk), 
            .CD(sync_reset), .Q(stop_assert[0]));   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(123[22:37])
    defparam stop_assert_58__i0.GSR = "ENABLED";
    PFUMX i460 (.BLUT(n548), .ALUT(n549), .C0(cs_gddr_sync[0]), .Z(n550));
    FD1P3DX cs_gddr_sync_i0 (.D(n74[0]), .SP(sync_clk_enable_6), .CK(sync_clk), 
            .CD(sync_reset), .Q(cs_gddr_sync[0])) /* synthesis syn_preserve=1, LSE_LINE_FILE_ID=5, LSE_LCOL=33, LSE_RCOL=70, LSE_LLINE=348, LSE_RLINE=349 */ ;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(105[3] 137[6])
    defparam cs_gddr_sync_i0.GSR = "ENABLED";
    LUT4 i458_then_4_lut (.A(ns_gddr_sync_2__N_19[1]), .B(cs_gddr_sync_c[1]), 
         .C(reset_flag), .D(cs_gddr_sync[2]), .Z(n549)) /* synthesis lut_function=(A (C)+!A (B (C+!(D))+!B (C))) */ ;
    defparam i458_then_4_lut.init = 16'hf0f4;
    LUT4 i458_else_4_lut (.A(\ns_gddr_sync_2__N_22[2] ), .B(cs_gddr_sync_c[1]), 
         .C(reset_flag), .D(cs_gddr_sync[2]), .Z(n548)) /* synthesis lut_function=(A (C)+!A (B (C)+!B !((D)+!C))) */ ;
    defparam i458_else_4_lut.init = 16'he0f0;
    LUT4 i343_2_lut_rep_12 (.A(ctrl_cnt[3]), .B(n172), .Z(sync_clk_enable_5)) /* synthesis lut_function=(!(A (B))) */ ;
    defparam i343_2_lut_rep_12.init = 16'h7777;
    LUT4 i229_3_lut (.A(ctrl_cnt[1]), .B(n172), .C(ctrl_cnt[0]), .Z(n14[1])) /* synthesis lut_function=(!(A ((C)+!B)+!A !(B (C)))) */ ;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(105[3] 137[6])
    defparam i229_3_lut.init = 16'h4848;
    LUT4 i113_3_lut (.A(reset_flag), .B(ns_gddr_sync_2__N_19[1]), .C(cs_gddr_sync_c[1]), 
         .Z(n174)) /* synthesis lut_function=(A (B (C))+!A (B (C)+!B !(C))) */ ;   // d:/bicubicshared/latest/latticefpga/ecp5_lvds/ip_gddr71tx_12lane/ip_gddr71tx_12lane.v(143[3] 208[10])
    defparam i113_3_lut.init = 16'hc1c1;
    LUT4 ctrl_cnt_0__bdd_4_lut (.A(ctrl_cnt[2]), .B(reset_flag), .C(ctrl_cnt[3]), 
         .D(ctrl_cnt[1]), .Z(n551)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ;
    defparam ctrl_cnt_0__bdd_4_lut.init = 16'h0800;
    
endmodule
